Currently, a gate driving device is formed on an array substrate of a liquid crystal displayer by using an array process, i.e. a gate driver on array (GOA) process. A conventional gate drive device usually comprises a plurality of cascaded shift registers, and a signal outputted from a signal outputting terminal of the shift register in each stage is generally controlled by a pulling-up node and a clock signal. However, in a conventional shift register, during a holding phase of the signal outputting terminal (Output), a cut-off voltage for a gate of a thin film transistor in an outputting circuit comprising a clock signal terminal (CLK) is −8V, and the Output terminal is also pulled down to −8V by a low level signal terminal (Vss). In this manner, a voltage difference (Vgs) between the gate and the source of the thin film transistor is 0V. According to a transfer characteristic curve of a switch transistor, when the Vgs of the switch transistor is −8V, the switch transistor is turned off perfectly, i.e. it is equivalent to an open circuit. However, a leakage current will be large at a high temperature, resulting in the signal outputted from the Output terminal fluctuating with a high level of CLK terminal during a period in which the signal is supposed to be turned off. This will cause an abnormal display. Furthermore, it is difficult to make the transfer characteristic curve drift rightward by a traditional production process.